In recent years, an active matrix semiconductor display device is attracting attentions in the market as a flat panel display (FPD). In particular, a self-luminous type active matrix display device using a self-luminous material such as an organic EL is attracting attentions and actively researched and developed as a flat panel display substituting a liquid crystal display (LCD).
An active matrix display device is known to be operated by an analog gray scale method in which luminance of each pixel is continuously changed or a digital gray scale method in which luminance of each pixel is pervasively changed. The analog gray scale method is realized by continuously changing a voltage applied to a light emitting element such as an EL element provided in each pixel to continuously change the luminance of the light emitting element. The digital gray scale method includes an area gray scale method in which a plurality of light emitting elements (or sub-pixels) having different areas are provided in each pixel and the combination of the light emitting elements to emit light is changed, thereby the luminance of each pixel is changed, and a time gray scale method in which one light emitting element is provided in each pixel and the light emission time of the light emitting element in one frame period (a period to display one image) is pervasively changed to change the luminance of each pixel. Further, it is widely known that a color display is performed by using a filter of red (R), green (G), or blue (B) for each pixel.
In the area gray scale method, a plurality of sub-pixels are provided in each pixel. For example, in the case where k sub-pixels E1, E2, . . . , and Ek are provided in each pixel (the number of bits is k) and the area of the smallest sub-pixel is E0, the luminance of each pixel can be changed in 2k gray scale levels with the luminance corresponding to E0 as a minimum unit by designing so as to satisfy E1=1×E0, E2=2×E0, . . . , and Ek=2k−1×E0.
In the time gray scale method, one frame period is divided into a plurality of (for example, k) sub-frame periods S1, S2, . . . , and Sk. When setting the shortest light emission period as T0 and other light emission periods as T1=1×T0, T2=2×T0, . . . , and Tk=2k−1×T0 (the sum of the periods T1 to Tn is shorter than one frame period), the luminance of each pixel can be changed in 2k gray scale levels with the luminance corresponding to T0 as a minimum unit by changing the combination (i.e., selecting light emission/non-light emission of each pixel in each light emission period).
Such a display device of the time gray scale method requires a control circuit (panel controller) for converting inputted video data (or digital video signals) into a format of the time gray scale method and supplying the converted video data to a display panel at an appropriate timing (see Patent Document 1). FIG. 1 shows an example of the display device of the time gray scale method provided with such a panel controller.
A display device 1 in FIG. 1 includes a display panel 2 and a panel controller 3 to which a video data is inputted. The panel controller 3 includes a format converter portion 4 which converts the inputted video data into a format of the time gray scale method, a first video memory 5 and a second video memory 6, which store the converted video data which is converted in the format converter portion 4, and a display control portion 7 which reads the video data stored in the first video memory 5 and the second video memory 6 and transmits it to the display panel 2. The format converter portion 4 is connected to the first video memory 5 and the second video memory 6 through tri-state buffers 8 and 9 and the display control portion 7 is connected to the first video memory 5 and the second video memory 6 through a selector 10. The format converter portion 4 and the display control portion 7 are connected to each other so that they can operate in synchronization.
In the panel controller 3, the video data converted in the format converter portion 4 is written to the first video memory 5 in a certain frame period while video data converted in format which is stored in the second video memory 6 is read out to the display control portion 7 and transmitted to the display panel 2. In the next frame period, video data is written to the second video memory 6 and video data is read out from the first video memory 5 and transmitted to the display panel 2. The aforementioned operations are repeated alternately. That is, the first video memory 5 and the second video memory 6 are switched in turn to be used per frame. An SRAM can be preferably used as the first video memory 5 and the second video memory 6.
In recent years, however, the amount of video data tends to increase according to the increasing size of the display panel, and there is a case where video data of one frame is not stored in one SRAM. In view of this, a plurality of SRAMs are required to be provided for each of the first video memory 5 and the second video memory 6, which is not preferable for downsizing and cost reduction of a product.
On the other hand, a light emitting element such as an EL element is deteriorated by long time of light emission. Therefore, when a display device using an EL element is used for a long time, luminance characteristics of EL elements vary according to the deterioration of each EL element. That is, the deteriorated EL element and an EL element which is not deteriorated vary in luminance even when the same voltage is applied thereto.
In order to prevent such luminance variations, there is a deterioration compensation circuit which corrects the video data signal for driving the pixel of which EL element is deteriorated so as to compensate for the deterioration of the EL element by detecting the light emission time of the EL element in each pixel by regularly sampling a video data signal, and comparing the accumulation of the detected value and data on change with time of luminance characteristics of the EL element which is stored in advance (see Patent Document 2).
FIG. 2 is a block diagram showing an example of such a deterioration compensation circuit. A deterioration compensation circuit 20 in FIG. 2 includes a counter portion 21, a memory circuit portion 22, and a signal correction portion 23. The counter portion 21 includes a counter 12, the memory circuit portion 22 includes a volatile memory 13 and a nonvolatile memory 14, and the signal correction portion 23 includes a correction circuit 15 and a correction data storing portion 16. In this deterioration compensation circuit 20, video data for driving a pixel of which EL element is deteriorated in a first video signal 11A as video data before correction is corrected in the signal correction potion 23 and supplied as a second video signal 11B as video data after correction to a display device 17.
In specific, the first video signal 11A is regularly (for example, per second) sampled in this deterioration compensation circuit 20 and the counter 12 counts the light emission and non-light emission of each pixel by the sampled signal. The counted number of light emission of each pixel, that is the accumulated light emission time (hereinafter referred to as accumulated time data) is sequentially stored in the memory circuit portion 22. The number of light emission is accumulated, therefore, the memory circuit portion is preferably formed using a nonvolatile memory. However, the number of writing to the nonvolatile memory is generally limited, therefore, data is written to the volatile memory 13 in operation of the display device 17 while the data is written to the nonvolatile memory 14 at a certain interval (for example, per hour, at shutdown of a power source, or the like). At shutdown of the power source, the data in the volatile memory 13 is lost, however, the accumulated time data is read out from the nonvolatile memory 14 to the volatile memory 13 when the power source is turned on later again, and thus the counting of the accumulated light emission time of an EL element is continued.
In the correction data storing portion 16 of the signal correction portion 23, data on change with time of luminance characteristics of the EL element is stored in advance as a map for correcting video signals. The correction circuit 15 compares the map for correcting video signals and the accumulated light emission time of each pixel which is read out from the volatile memory 13, and increases or decreases a digital video signal (pixel data) of each pixel according to the degree of deterioration of each pixel figured out from the accumulated light emission time, thereby the inputted first video signal 11A is corrected.
When the amount of video data is increased in such a deterioration compensation circuit 20, the amount of data to be transferred by the counter 12, the volatile memory 13, the nonvolatile memory 14, the correction circuit 15 and the like is increased, thereby these components are more frequently accessed. Accordingly, a component (especially a memory) capable of fast speed operation is required, which leads to increase the cost.
[Patent Document 1]    Japanese Patent Laid-Open No. 2004-163919
[Patent Document 2]    Japanese Patent Laid-Open No. 2002-175041